In the production of semiconductor devices, wafers of semiconductor material may be doped with at least one dopant by ion implantation. This process invariably damages the implanted surface. It is desirable to remove this damage so as to present a high quality surface for subsequent processing steps, such as metallization. This is typically achieved by subjecting the implanted wafer to annealing which simultaneously activates the implanted ions.
Conventional long-term furnace annealing leads to a high-quality surface. Unfortunately, the furnace annealing is time and energy consuming, and may result in dopant profile broadening as well as the loss of volatile components (e.g. As from GaAs wafers or P from InP wafers) requiring maintenance of a specific atmosphere over a sample being annealed to compensate for the loss of the volatile component.
Lately, Rapid Thermal Annealing (RTA) is becoming increasingly useful in the processing of implanted semiconductors, especially of semiconductors comprising III-V and II-V compound semiconductors, including such as GaAs and InP and compound semiconductors lattice-matched to GaAs and InP such as InGaAs, InGaAsP, AlInAs, AlInAsP, etc. In the RTA process, the object being annealed is exposed to heat energy at high temperatures of up to 1100.degree. C. for short periods of time such as from 1 to 30 seconds or more. For example, InP wafers are subjected to temperatures ranging from 700.degree. to 800.degree. C. while GaAs wafers are annealed at temperatures ranging from 800.degree. to 1050.degree. C.
The RTA method offers the advantage of removing the implantation damage with less dopant profile broadening compared to conventional furnace annealing. However, the RTA process is conducive to slip line formation as well as EN1 traps during the RTA.
Slip lines are regions of a wafer resulting from the introduction of thermoelastic stresses arising from high temperature exposure during the RTA and giving rise to thermoplastic phenomena involving dislocation glide. Since in the RTA method, the cooling of the sample takes place primarily by radiation, thermal gradients can occur due to variation in radiation intensity from different parts of the sample. For example, the edge of the wafer cools faster than the center due to the comparatively higher radiation from it. As a result, thermal stresses leading to the slip lines can be created by the thermal gradient in the wafer. G. Bentini, L. Correra and C. Donolato in "Defects Introduced in Silicon Wafers During Rapid Isothermal Annealing: Thermoelastic and Thermoplastic Effects", J. App. Phys. 56 (10), 15 Nov. 1984, pp. 2922-2929, describe formation of slip lines in silicon. This phenomena occurs in III-V and II-VI semiconductor materials as well. Very often, the slip lines may extend for a considerable distance into the central area of semiconductor wafers, such as 1.3 cm. (0.5 inches) or more from an edge of a wafer about 5 or 7.6 cm. (2.0 or 3.0 inches, respectively) in diameter, resulting in regions which are not suitable for further processing, thus leading to poor device yield.
Additionally, EN1 traps may be introduced at higher RTA temperatures. In such compound semiconductors as n-GaAs the EN1 traps are typically introduced by RTA above 800.degree. C. The EN1 trap is an electron trap with a certain activation energy from the conduction band and results from infrared heating during the RTA. This trap formation is closely related to a rapid heating stage in the RTA process and is never observed after conventional furnace annealing. For more detailed discussion of EN1 traps, see M. Kazuhara and T. Nozaki, "Study of Electron Traps in n-GaAs Resulting From Infrared Rapid Thermal Annealing", J. Appl. Phys. 59 (9), 1 May 1986, pp. 3131-3136. The formation of electron traps in n-GaAs from RTA has been studied using deep level transient spectroscopy. It has been reported by these authors that in addition to a number of trap levels generally present in as-grown bulk GaAs, a new trap EN1 with an activation energy of 0.20 eV from the conduction band and an electron capture cross section of 5.4.times.10.sup.-16 cm.sup.2, is formed in encapsulated GaAs annealed at 950.degree. C. in an RTA.
It is important that the wafers annealed by RTA should possess not only reproducibly high mobilities and uniform activation, but should also be of morphological quality at least comparable to that obtained with the conventional furnace annealing. Thus, it is desirable to be able to subject the implanted semiconductor wafers to RTA while at the same time obtaining a high quality surface without any slip lines. Additionally, it is desirable to substantially avoid presence of EN1 trapped defects in the RTA treated wafers. These problems have been overcome in a manner described hereinbelow.